A non-volatile memory with the use of a polarization reversible ferroelectric material by an opposite polarity of an applied voltage has equal information write-in time and information read-out time in principle. Moreover the standstill condition (backup time) can maintain polarization (residual polarization) even with no applied voltage, so that the non-volatile memory appears to be ideal.
Previously, semiconductor non-volatile memories having ferroelectric capacitors have been proposed wherein a ferroelectric capacitor is located on a silicon (Si) substrate (See U.S. Pat. No. 4,149,302), and having a ferroelectric film located on an MIS-type transistor gate electrode (See U.S. Pat. No. 3,832,700).
A typical non-volatile memory cell, as shown in FIG. 8, generally has a circuit construction with an N-type MOS transistor Tr having a gate electrode G connected to word line W. A drain electrode D is connected to a bit line B, and a source electrode S is connected to one electrode of a ferroelectric capacitor C. The other electrode of the ferroelectric capacitor C is connected to a plate line P. An example of a semiconductor structure for such a memory cell is shown in FIG. 9. The semiconductor structure shown in FIG. 9 has an N-type MOS transistor Tr. Transistor Tr comprises a polysilicon (polycrystalline silicon) gate electrode 3 formed over a gate oxide film 2 on a P-type silicon substrate 1, a high concentration N-type source region 4 and a drain region 5 diffused and formed in the silicon substrate 1 by self-alignment, and a ferroelectric capacitor C formed on an interlayer insulating film 7 such as phosphorus glass on an element separating local oxide film (LOCOS) 6. The ferroelectric capacitor C on the interlayer insulating film 7 is formed by successively laminating a lower electrode 8 such as platinum (Pt), a ferroelectric film 9 such as PZT and an upper electrode 10 such as aluminum (Al). The source region 4 and the upper electrode 10, as high concentration diffusion regions, are connected to a wiring 12 of Al via a contact hole 11. A second interlayer insulating film 13 such as phosphorus glass is located over transistor Tr.
In forming the ferroelectric capacitor C via the interlayer insulating film 7 on the local oxide film 6, the ferroelectric capacitor C is formed by effectively utilizing a space on the local oxide film 6. However, the length of the wiring 12 from the source region 4 to the upper electrode 10 is redundant and increases the size of the area occupied by the memory cell. While a memory cell of this structure results in an increase of the cell area, it can be said to be realistic structure for the reason mentioned below. FIG. 10 shows an example of a memory cell structure wherein a ferroelectric film 9 is located directly on a source region. A polysilicon upper electrode wiring 14 was formed on the ferroelectric film 9, and the source region 4 itself acts as a lower electrode. After forming the ferroelectric film 9, however, it was necessary to apply an oxygen anneal to improve the crystallizability of the film and to enhance the specific dielectric constant .epsilon..sub.r. Because of the strong reactivity of oxygen in the oxygen anneal step, a silicon oxide film (SiO.sub.2) 15 inevitably forms between the source region 4 and the ferroelectric film 9. When this film 15 is very thin, as shown in FIG. 11(A), the silicon oxide film 15 becomes a series contact resistance R.sub.O. The presence of this parasitic contact resistance R.sub.O occasions a delay in access time. Moreover, when the film 15 is relatively thick, the film 15 becomes a series parasitic capacitor C.sub.O as shown in FIG. 11(B). In such a case, memory capacity is the result of the synthetic capacity of the parasitic capacitor C.sub.O and the ferroelectric capacitor C in series. However, to this parasitic capacitor C.sub.O is applied a partial tension of the source voltage. In order to prevent the silicon oxide film 15 from dielectric breakdown due to the partial tension, it is necessary to either form a considerably thicker film or to suppress the partial tension itself. However, if the silicon oxide film 15 is made considerably thicker, its partial tension also becomes large, so that pressure resistivity is not effectively improved. Moreover, in order to directly suppress partial tension, it is necessary to either make the silicon oxide film 15 very thin or to make the ferroelectric film 9 considerably thicker. However, it is difficult to make the silicon oxide film 15 very thin owing to the above-described oxygen anneal treatment, while the considerably thicker ferroelectric film 9 means a lower capacitance for the ferroelectric capacitor C, and as a result, the ferroelectric capacitor cannot perform its function. For such reasons, the structure (circuitry) shown in FIG. 8 is useful as a non-volatile memory structure for sufficiently bringing out the function of a ferroelectric capacitor. However, as stated above, the structure has the problem of utilizing a large cell area.
Therefore, the present invention takes the problems of each of the above structures into consideration, and provides a semiconductor device having a ferroelectric device, without spoiling the function of a non-volatile memory using a ferroelectric material and without increasing the memory cell area for a ferroelectric capacitor. The present invention also discloses a method of manufacturing the same.